The present invention is an improved method and apparatus for bringing locally regenerated clock signals, distributed among multiple loads, into time alignment with a reference clock signal. The improvement minimizes start-up time from reset and prevents instability in achieving synchronization in phase-locked loop circuits employing an analog, variable delay line. The invention overcomes the limitation of such circuits which require minimum phase delay time to be less than one-half period of the clock signal and permits operation at frequencies up to the highest that can be passed along the delay line. Frequencies several times those currently used in high speed computers, whose speeds can be of the order of 10 million instructions per second, are easily accommodated.
In a high-speed, multiple chip synchronous computer, the clock signal must be delivered to all chips very carefully. The skew or difference in time between the significant edges of clock signals in different parts of the system typically must be held to one nanosecond or less. A distributed system for regeneration of powerful clock signals from a lower-power master reference signal is more desirable than a central clock because of the very large amount of power required. The regeneration must be performed at all sites in the computer and in the presence of amplification stages so that all regenerated clock signals are produced with minimum skew. Phase-locked loop circuits using a voltage controlled oscillator, phase-frequency detector and an analog, variable delay line delay have typically been used to synchronize computer clocks. Phase locked loop circuits using a variable delay line are referred to herein as a "delay locked loop" circuits.
The delay locked loop, which uses an analog delay line based on a sequence of voltage-controlled delay elements, is the simpler, more versatile approach to a clock regeneration circuit. The delay locked loop circuit detects the phase difference between clock signals of the same frequency and produces an error voltage varying with the phase difference. By feeding back such voltage to control a variable delay line, the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of the reference signal. Conventional delay locked loop circuits have a major drawback. Any delay line and amplifier will have a minimum achievable delay when the control voltage is maximum. In systems where the clock signal is derived from the reference signal, if the clock frequency is raised until a one-half period is slightly less than the minimum achievable delay, the phase detector will cause the system to seek a faster operating point at less delay. This clearly can not be reached. Only certain bands of higher frequencies will allow stable-from-reset synchronization, for example when minimum delay equals one and one-half periods.
The problem of providing a clock regeneration system which will achieve stable lock in the shortest time, irrespective of whether the phase of the local clock signal is leading or lagging relative to the phase of the reference clock, has been a major challenge to designers in the high-speed computer field. The enhancement of circumventing the minimum delay problem without sacrificing resolution of the delay line circuit and without adding a prohibitive number of stages would satisfy a long felt need in the computer industry.